103 lines
3.3 KiB
C
103 lines
3.3 KiB
C
// ws2812_init.c
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// C-based helper function for initilalizing
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// the I2S system
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#include <string.h>
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#include "slc_register.h"
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#include "user_interface.h"
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#include "ws2812_defs.h"
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#include "ws2812_dma.h"
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#if WS2812_USE_INTERRUPT == 1
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// for debugging purposes
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static volatile uint32_t interrupt_count = 0;
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static void ws2812_isr(void)
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{
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//clear all intr flags
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WRITE_PERI_REG(SLC_INT_CLR, 0xffffffff);//slc_intr_status);
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interrupt_count++;
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}
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#endif
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void ws2812_dma(sdio_queue_t *i2s_pixels_queue)
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{
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// Reset DMA
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SET_PERI_REG_MASK(SLC_CONF0, SLC_RXLINK_RST); //|SLC_TXLINK_RST);
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CLEAR_PERI_REG_MASK(SLC_CONF0, SLC_RXLINK_RST); //|SLC_TXLINK_RST);
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// Clear DMA int flags
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SET_PERI_REG_MASK(SLC_INT_CLR, 0xffffffff);
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CLEAR_PERI_REG_MASK(SLC_INT_CLR, 0xffffffff);
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// Enable and configure DMA
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CLEAR_PERI_REG_MASK(SLC_CONF0,(SLC_MODE<<SLC_MODE_S));
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SET_PERI_REG_MASK(SLC_CONF0,(1<<SLC_MODE_S));
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SET_PERI_REG_MASK(SLC_RX_DSCR_CONF,SLC_INFOR_NO_REPLACE|SLC_TOKEN_NO_REPLACE);
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CLEAR_PERI_REG_MASK(SLC_RX_DSCR_CONF, SLC_RX_FILL_EN|SLC_RX_EOF_MODE | SLC_RX_FILL_MODE);
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// configure DMA descriptor
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CLEAR_PERI_REG_MASK(SLC_RX_LINK,SLC_RXLINK_DESCADDR_MASK);
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SET_PERI_REG_MASK(SLC_RX_LINK, ((uint32)i2s_pixels_queue) & SLC_RXLINK_DESCADDR_MASK);
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#if WS2812_USE_INTERRUPT == 1
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// Attach the DMA interrupt
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ets_isr_attach(ETS_SLC_INUM, (int_handler_t)ws2812_isr , (void *)0);
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//Enable DMA operation intr
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// WRITE_PERI_REG(SLC_INT_ENA, SLC_RX_EOF_INT_ENA);
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//clear any interrupt flags that are set
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WRITE_PERI_REG(SLC_INT_CLR, 0xffffffff);
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///enable DMA intr in cpu
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ets_isr_unmask(1<<ETS_SLC_INUM);
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#endif
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//Start transmission
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SET_PERI_REG_MASK(SLC_RX_LINK, SLC_RXLINK_START);
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//Init pins to i2s functions
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0RXD_U, FUNC_I2SO_DATA);
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//Enable clock to i2s subsystem
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i2c_writeReg_Mask_def(i2c_bbpll, i2c_bbpll_en_audio_clock_out, 1);
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//Reset I2S subsystem
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CLEAR_PERI_REG_MASK(I2SCONF,I2S_I2S_RESET_MASK);
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SET_PERI_REG_MASK(I2SCONF,I2S_I2S_RESET_MASK);
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CLEAR_PERI_REG_MASK(I2SCONF,I2S_I2S_RESET_MASK);
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//Select 16bits per channel (FIFO_MOD=0), no DMA access (FIFO only)
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CLEAR_PERI_REG_MASK(I2S_FIFO_CONF, I2S_I2S_DSCR_EN|(I2S_I2S_RX_FIFO_MOD<<I2S_I2S_RX_FIFO_MOD_S)|(I2S_I2S_TX_FIFO_MOD<<I2S_I2S_TX_FIFO_MOD_S));
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//Enable DMA in i2s subsystem
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SET_PERI_REG_MASK(I2S_FIFO_CONF, I2S_I2S_DSCR_EN);
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//trans master&rece slave,MSB shift,right_first,msb right
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CLEAR_PERI_REG_MASK(I2SCONF, I2S_TRANS_SLAVE_MOD|
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(I2S_BITS_MOD<<I2S_BITS_MOD_S)|
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(I2S_BCK_DIV_NUM <<I2S_BCK_DIV_NUM_S)|
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(I2S_CLKM_DIV_NUM<<I2S_CLKM_DIV_NUM_S));
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SET_PERI_REG_MASK(I2SCONF, I2S_RIGHT_FIRST|I2S_MSB_RIGHT|I2S_RECE_SLAVE_MOD|
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I2S_RECE_MSB_SHIFT|I2S_TRANS_MSB_SHIFT|
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(((WS_I2S_BCK-1)&I2S_BCK_DIV_NUM )<<I2S_BCK_DIV_NUM_S)|
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(((WS_I2S_DIV-1)&I2S_CLKM_DIV_NUM)<<I2S_CLKM_DIV_NUM_S));
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#if WS2812_USE_INTERRUPT == 1
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//clear int
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SET_PERI_REG_MASK(I2SINT_CLR, I2S_I2S_RX_WFULL_INT_CLR|I2S_I2S_PUT_DATA_INT_CLR|I2S_I2S_TAKE_DATA_INT_CLR);
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CLEAR_PERI_REG_MASK(I2SINT_CLR, I2S_I2S_RX_WFULL_INT_CLR|I2S_I2S_PUT_DATA_INT_CLR|I2S_I2S_TAKE_DATA_INT_CLR);
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//enable int
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SET_PERI_REG_MASK(I2SINT_ENA, I2S_I2S_RX_REMPTY_INT_ENA|I2S_I2S_RX_TAKE_DATA_INT_ENA);
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#endif
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//Start transmission
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SET_PERI_REG_MASK(I2SCONF,I2S_I2S_TX_START);
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}
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// end of file
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